revision 1.1 jan. 2004 1 r0 201-STC62WV12816 very low power/voltage cmos sram 128k x 16 bit ? wide vcc operation voltage : 2.4v ~ 5.5v ? very low power consumption : vcc = 3.0v c-grade: 29ma (@55ns) operating current i -grade: 30ma (@55ns) operating current c-grade: 24ma (@70ns) operating current i -grade: 25ma (@70ns) operating current 0.3ua(typ.) cmos standby current vcc = 5.0v c-grade: 60ma (@55ns) operating current i -grade: 62ma (@55ns) operating current c-grade: 53ma (@70ns) operating current i -grade: 55ma (@70ns) operating current 1.0ua(typ.) cmos standby current ? high speed access time : -55 55ns -70 70ns ? automatic power down when chip is deselected ? three state outputs and ttl compatible the stc 62wv12816 is a high performance , very low power cmos static random access memory organized as 131,072 words by 16 bits and operates from a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 0.3ua at 3.0v /25 o c and maximum access time of 55ns at 3.0v/ 85 o c. easy memory expansion is provided by active low chip enable (ce), active low output enable(oe) and three-state output drivers. t he STC62WV12816 h as a n automatic pow er down feature, reducing the power consumption significantly when chip is deselected. the STC62WV12816 is available in d ice form , jedec standard 44-pin tsop type ii package and 48-ball bga package. ? description ? features ? block diagram ? product family ? pin configurations stc international limited . reserves the right to modi fy document contents without notice. STC62WV12816 speed ( ns ) standby ( i ccsb1 , max ) operating ( i cc , max ) product family operating temperature vcc range vcc=3.0v vcc=3.0v pkg type STC62WV12816dc dice STC62WV12816ec tsop2-44 STC62WV12816ac +0 o c to +70 o c 2.4v ~5.5v 55/70 3.0ua 53ma bga-48-0608 STC62WV12816di dice STC62WV12816ei tsop2-44 STC62WV12816ai -40 o c to +85 o c 2.4v ~ 5.5v 55/70 5.0ua 25ma bga-48-0608 stc row decoder memory array 1024 x 2048 column i/o write driver sense amp column decoder data buffer output a3 a2 a1 data buffer input control gnd vcc oe we ce dq15 dq0 a16 a5 a6 a7 a15 a13 16 16 16 16 14 128 2048 1024 20 a14 a12 a9 a4 a0 a11 a8 address input buffer a10 address input buffer . . . . ub . . . . lb g h f e d c b a 123456 d15 d14 vss d9 d8 lb vcc n.c. a8 a9 d13 a12 a14 d12 d11 d10 a5 ub oe a3 a0 a11 a10 a13 a15 we d5 a16 a7 a6 d4 d3 d1 d7 d6 d2 a4 a1 a2 d0 n.c. vss vcc n.c. ce n.c. n.c. n.c. ? i/o configuration x8/x16 selectable by lb and ub pin 24ma 55ma 70ns 70ns power dissipation 55ns: 3.0~5.5v 70ns: 2.7~5.5v ? easy expansion with ce and oe options a4 a3 a2 a1 a0 ce dq0 dq1 dq2 dq3 vcc gnd dq4 dq5 dq6 dq7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb dq15 dq14 dq13 dq12 gnd vcc dq11 dq10 dq9 dq8 nc a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 62wv12816ec 62wv12816ei ? data retention supply voltage as low as 1.5v ? fully static operation vcc=5.0v vcc=5.0v 10ua 30ua .com .com .com
revision 1.1 jan. 2004 2 r0 201-STC62WV12816 ? pin descriptions stc STC62WV12816 name function a0-a16 address input these 17 address inputs select one of the 131,072 x 16-bit words in the ram. ce chip enable input we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. lb and ub data byte control input lower byte and upper byte data input/output control pins. dq0 - dq15 data input/output ports these 16 bi-directional ports are used to read data from or write data into the ram. vcc power supply gnd ground ? truth table ce is active low. chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. mode ce we oe lb ub d0~d7 d8~d15 vcc current h x x x x high z high z i ccsb , i ccsb1 not selected (power down) x x x h h high z high z i ccsb , i ccsb1 output disabled l h h x x high z high z i cc l l dout dout i cc h l high z dout i cc read l h l l h dout high z i cc ll din din i cc hl x din i cc write l l x lh din x i cc l xx h h high z high z i cc .com .com .com .com
revision 1.1 jan. 2004 3 r0 201-STC62WV12816 symbol parameter test conditions min. typ. (1) max. units v dr vcc for data retention ce R R Q R R Q R R Q .com .com .com .com
revision 1.1 jan. 2004 4 r0 201-STC62WV12816 jedec parameter name parameter name description cycle time : 55ns (vcc = 3.0~5.5v) (vcc = 2.7~5.5v) unit t avax t rc read cycle time 55 -- -- 70 -- -- ns t avqv t aa address access time -- -- 55 -- -- 70 ns t elqv t acs chip select access time (ce) -- -- 55 -- -- 70 ns t ba t ba data byte control access time (lb,ub)----30----35 ns t glqv t oe output enable to output valid -- -- 30 -- -- 35 ns t e1lqx t clz chip select to output low z (ce) 10 -- -- 10 -- -- ns t be t be data byte control to output low z (lb,ub)10----10---- ns t glqx t olz output enable to output in low z 5----5---- ns t ehqz t chz chip deselect to output in high z (ce) -- -- 30 -- -- 35 ns t bdo t bdo data byte control to output high z (lb,ub) -- -- 30 -- -- 35 ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t axox t oh data hold from address change 10 -- -- 10 -- -- ns ? ac electrical characteristics ( ta = -40 to + 85 o c ) read cycle ? ac test conditions (test load and input/output reference) ? key to switching waveforms waveform inputs outputs must be steady may change from h to l don t care: any change permitted does not apply must be steady will be change from h to l change : state unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , ? low v cc data retention waveform ( ce controlled ) ce data retention mode vcc t cdr vcc t r v ih v ih vcc v dr 1.5v tc STC62WV12816 (1) 1. t ba is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; t ba is 55ns/70ns (@speed=55ns/70ns) without address toggle. note : min. typ. max. min. typ. max. input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc output load c l = 100pf+1ttl c l = 30pf+1ttl cycle time : 70ns .com .com .com .com
revision 1.1 jan. 2004 5 r0 201-STC62WV12816 stc STC62WV12816 ? switching waveforms (read cycle) read cycle1 (1,2,4) t rc t oh t aa d out address t oh notes: 1. we is high for read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. the parameter is guaranteed but not 100% tested. t oh read cycle3 (1,4) t rc t oe d out lb,ub ce oe address t clz (5) t acs t chz (1,5) t ohz (5) t olz t aa read cycle2 (1,3,4) t clz t chz (5) d out lb,ub ce (5) t ba t acs t be t bdo t bdo t ba t be .com .com .com .com
revision 1.1 jan. 2004 6 stc STC62WV12816 r0 201-STC62WV12816 ? switching waveforms (write cycle) jedec parameter name parameter name description cycle time : 55ns (vcc = 3.0~5.5v) (vcc = 2.7~5.5v) unit t avax t wc write cycle time 55 -- -- 70 -- -- ns t e1lwh t cw chip select to end of write 55 -- -- 70 -- -- ns t avwl t as address setup time 0----0---- ns t avwh t aw address valid to end of write 55 -- -- 70 -- -- ns t wlwh t wp write pulse width 30 -- -- 35 -- -- ns t whax t wr write recovery time (ce,we) 0----0---- ns t bw t bw date byte control to end of write (lb,ub)25----30---- ns t wlqz t whz write to output in high z -- -- 25 -- -- 30 ns t dvwh t dw data to write time overlap 25 -- -- 30 -- -- ns t whdx t dh data hold from write time 0----0---- ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t whox t ow end of write to output active 5----5---- ns ? ac electrical characteristics ( ta = -40 to + 85 o c ) write cycle 1. t bw is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; t bw is 55ns/70ns (@speed=55ns/70ns) without address toggle. (1) note : (ce) min. typ. max. min. typ. max. t wr write cycle1 (1) t wc (3) t cw (11) t bw (2) t wp t aw t ohz (4,10) t as (3) t dh t dw d in d out we lb,ub ce oe address (5) cycle time : 70ns .com .com .com .com
revision 1.1 jan. 2004 7 r0 201-STC62WV12816 stc STC62WV12816 write cycle2 (1,6) t wc t cw (11) (2) t wp t aw t whz (4,10) t as t wr (3) t dh t dw d in d out we ce address (5) t ow (7) (8) (8,9) t bw lb,ub notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low to the end of write. .com .com .com .com
revision 1.1 jan. 2004 8 r0 201-STC62WV12816 ? ordering information stc STC62WV12816 ? package dimensions 48 mini-bga (6 x 8) d1 view a 1.4 max. e e1 1: controlling dimensions are in millimeters. 2: pin#1 dot marking by laser or pad print. 3: symbol "n" is the number of solder balls. ball pitch e = 0.75 d 8.0 6.0 en 48 3.75 e1 d1 5.25 notes: note: stc (stc international limited.) assumes no responsibility for t he application or use of a ny product or circuit described he rein. stc does not authorize its products for use as cr itical components in any application in which the failu re of the stc product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. STC62WV12816 x x y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material -: normal g: green p: pb free package e: tsop2-44 a: bga-48-0608 d: dice .com .com .com .com
revision 1.1 jan. 2004 9 r0 201-STC62WV12816 stc STC62WV12816 ? package dimensions tsop2-44 .com .com .com
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